PIIPM25P12B008
I27147 02 - Oct
Other DSP pins mapping
Symbol
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Enc1–Hall1 /
SpiCK
Enc2 – Hall2 /
SpiSTE
Strb – Hall3 /
SpiRx
SpiTx
Ref3.3V
5V supp.
Boot En~
Tx
Rx
LFAULT
LFAULT reset
FAULT~
RS~
Xtal1
PLLF1
PLLF2
PDPINTB
Signal Definition
OUT 1 high side IGBT gate drive signal
OUT 1 low side IGBT gate drive signal
OUT 2 high side IGBT gate drive signal
OUT 2 low side IGBT gate drive signal
OUT 3 high side IGBT gate drive signal
OUT 3 low side IGBT gate drive signal
Incremental Encoder 1 / Hall effect sensor
input 1/ SpiCK input (GND iso referenced)
Incremental Encoder 2 / Hall effect sensor
input 2 / SpiSTE input (GND iso referenced)
Incremental Encoder Strobe / Hall effect
sensor input 3 / SpiSIMO input (GND iso ref.)
SpiSOMI output (GND iso referenced)
3.3V reference voltage
Flash programming voltage pin
Boot ROM enable signal
SCI transmit data
SCI receive data
System general fault input (latched)
System general fault output reset signal
System general fault input (not latched)
DSP reset input signal (see also WD signal)
PLL oscillator input pin
PLL filter input 1
PLL filter input 2
External protection interrupt for EVB
DSP pin name ;pin N
PWM1;39
PWM2;37
PWM3;36
PWM4;33
PWM5;31
PWM6;28
SPICK;24
QEP1;57
SPISTE~;23
QEP2; 55
SPISIMO;21
CAP3; 52
SPISOMI;22
Vrefhi;82
Vcca; 83
Vccp;40
BOOT_EN~;86
SCITXD;17
CANTX ; 50
SCIRX ; 18
CANRX ; 49
IOPF6;92
IOPF5;89
PDPINTA~;6
RS~;93
XTAL1;87
PLLF;9
PLLF2;8
PDPINTB~;95
Comments
DSP Event Manager A output
DSP Event Manager A output
DSP Event Manager A output
DSP Event Manager A output
DSP Event Manager A output
DSP Event Manager A output
Optically isolated input
Optically isolated input
Optically isolated input
Optically isolated input
3.33V reference voltage for ADC converter
Supplied by the embedded flyback regulator
See also EDB electrical characteristics
Drives Tx+ and Tx- through an opto-isolator and a line driver
Driven by Rx+ and Rx- through an opto-isolator and a line driver
Activated by short circuits on output phases and DC bus minus and by
DC bus over-voltage comparator
LFAULT Reset signal, to be activated via software after a fault or
system boot
Activated by short circuits on output phases and DC bus minus and by
DC bus over-voltage comparator
Forces a DSP reset if WD signal holds too long (see also EDB
electrical char.)
A 10Mhz oscillator at 100ppm frequency stability feeds this pin.
PLL filter for 40Mhz DSP clock frequency
PLL filter for 40Mhz DSP clock frequency
Not used pull up 4.7K to 3.3V
~ indicates active low signals
www.irf.com
10
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